URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 49

Rev	Log message	Author	Age	Path
27	added sync simplex FIFO	unneback	4874d 11h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25	added sync FIFO	unneback	4875d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24	added vl_dff_ce_set	unneback	4876d 10h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23	fixed port map error in async fifo 1r1w	unneback	4877d 00h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22	added binary counters	unneback	4877d 05h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21	reg -> wire in and or mux in logic	unneback	4878d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18	naming convention vl_	unneback	4879d 13h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17		unneback	4943d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15	added delay line	unneback	4949d 10h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14	reg -> wire for various signals	unneback	4949d 15h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v