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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 50

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Rev Log message Author Age Path
50 added WB_B4RAM with byte enable unneback 4707d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 4707d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 4713d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 4809d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 4811d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 4814d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 4818d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42 updated mux_andor unneback 4822d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 4822d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 4823d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 4823d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 4829d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 4831d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4831d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4831d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 4844d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4851d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 4871d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 4871d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 4871d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 4872d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 4872d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 4873d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 4874d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 4875d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 4875d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 4876d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 4877d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 4941d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4947d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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