OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 65

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
65 RAM_BE system verilog version unneback 4904d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
64 SPR reset value unneback 4904d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4904d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4904d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4906d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
59 added WB RAM B3 with byte enable unneback 4907d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
56 WB B4 RAM we fix unneback 4936d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
55 added WB_B4RAM with byte enable unneback 4938d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
54 added WB_B4RAM with byte enable unneback 4938d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
53 added WB_B4RAM with byte enable unneback 4938d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
52 added WB_B4RAM with byte enable unneback 4938d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
51 added WB_B4RAM with byte enable unneback 4938d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
50 added WB_B4RAM with byte enable unneback 4938d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 4938d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 4945d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 5041d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 5043d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 5046d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 5050d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42 updated mux_andor unneback 5054d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 5054d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 5055d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 5055d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 5061d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 5062d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 5063d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 5063d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 5076d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 5083d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 5103d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.