URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 65

Rev	Log message	Author	Age	Path
40	new build environment with custom.v added as a result file	unneback	4828d 22h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39	added simple port prio based wb arbiter	unneback	4829d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38	updated andor mux	unneback	4829d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37	corrected polynom with length 20	unneback	4835d 15h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36	added generic andor_mux	unneback	4837d 00h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35	added vl_mux2_andor and vl_mux3_andor localparam	unneback	4837d 11h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34	added vl_mux2_andor and vl_mux3_andor	unneback	4837d 11h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33	updated wb3wb3_bridge	unneback	4850d 13h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32	added vl_pll for ALTERA (cycloneIII)	unneback	4857d 23h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31	sync FIFO updated	unneback	4877d 18h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v