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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 67

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67 support up to 8 wbm on arbiter unneback 3823d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
66 RAM_BE ack_o vector unneback 3861d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
65 RAM_BE system verilog version unneback 3861d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
64 SPR reset value unneback 3861d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3861d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3861d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3863d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
59 added WB RAM B3 with byte enable unneback 3864d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
56 WB B4 RAM we fix unneback 3893d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
55 added WB_B4RAM with byte enable unneback 3895d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
54 added WB_B4RAM with byte enable unneback 3895d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
53 added WB_B4RAM with byte enable unneback 3895d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
52 added WB_B4RAM with byte enable unneback 3895d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
51 added WB_B4RAM with byte enable unneback 3895d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
50 added WB_B4RAM with byte enable unneback 3895d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 3895d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 3902d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 3998d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 4000d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 4003d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 4007d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42 updated mux_andor unneback 4011d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 4011d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 4012d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 4012d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 4018d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 4019d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4019d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4019d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 4032d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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