OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 70

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
70 no arbiter in wb_b3_ram_be unneback 4640d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
69 no arbiter in wb_b3_ram_be unneback 4640d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
68 ram_be updated to optional mem_size unneback 4640d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
67 support up to 8 wbm on arbiter unneback 4641d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
66 RAM_BE ack_o vector unneback 4679d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
65 RAM_BE system verilog version unneback 4679d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
64 SPR reset value unneback 4679d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4679d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4680d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4681d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
59 added WB RAM B3 with byte enable unneback 4682d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
56 WB B4 RAM we fix unneback 4711d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
55 added WB_B4RAM with byte enable unneback 4714d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
54 added WB_B4RAM with byte enable unneback 4714d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
53 added WB_B4RAM with byte enable unneback 4714d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
52 added WB_B4RAM with byte enable unneback 4714d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
51 added WB_B4RAM with byte enable unneback 4714d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
50 added WB_B4RAM with byte enable unneback 4714d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 4714d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 4720d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 4817d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 4818d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 4821d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 4825d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42 updated mux_andor unneback 4829d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 4829d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 4830d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 4830d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 4836d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 4838d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.