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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 77

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52 added WB_B4RAM with byte enable unneback 4686d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
51 added WB_B4RAM with byte enable unneback 4686d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
50 added WB_B4RAM with byte enable unneback 4686d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 4686d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 4693d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 4789d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 4791d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 4794d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 4798d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42 updated mux_andor unneback 4802d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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