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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 78

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53 added WB_B4RAM with byte enable unneback 4095d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
52 added WB_B4RAM with byte enable unneback 4095d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
51 added WB_B4RAM with byte enable unneback 4095d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
50 added WB_B4RAM with byte enable unneback 4095d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 4095d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 4102d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 4198d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 4200d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 4203d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 4207d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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