URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 21

Rev	Log message	Author	Age	Path
21	reg -> wire in and or mux in logic	unneback	4878d 17h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18	naming convention vl_	unneback	4880d 04h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17		unneback	4943d 17h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15	added delay line	unneback	4950d 01h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14	reg -> wire for various signals	unneback	4950d 06h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13	cosmetic update	unneback	4950d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12	added wishbone comliant modules	unneback	4951d 04h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11	async fifo simplex	unneback	4951d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10	added dff_ce_clear	unneback	4953d 18h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8	added dff_ce_clear	unneback	4953d 18h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7	mem update	unneback	4953d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6	added library files	unneback	4966d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v