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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 21

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Rev Log message Author Age Path
21 reg -> wire in and or mux in logic unneback 4009d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4010d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4074d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4080d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4080d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4080d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4081d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4082d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4084d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4084d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 4084d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 4097d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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