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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 22

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Rev Log message Author Age Path
22 added binary counters unneback 3640d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3641d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3642d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3706d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3712d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3712d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3712d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3713d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3714d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 3716d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 3716d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 3716d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 3729d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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