OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 24

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 added vl_dff_ce_set unneback 4013d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4013d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4014d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4014d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4016d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4079d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4086d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4086d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4086d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4087d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4087d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4089d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4089d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 4089d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 4102d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.