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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 25

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Rev Log message Author Age Path
25 added sync FIFO unneback 3842d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 3844d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 3844d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 3844d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3845d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3847d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3910d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3917d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3917d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3917d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3918d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3918d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 3920d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 3920d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 3920d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 3933d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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