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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 25

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Rev Log message Author Age Path
25 added sync FIFO unneback 4872d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 4873d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4873d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4874d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4874d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4876d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4940d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4946d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4946d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4946d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4947d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4948d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4950d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4950d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 4950d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 4963d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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