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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 29

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Rev Log message Author Age Path
29 updated counter for level1 and level2 function unneback 3938d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 3939d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 3939d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 3939d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 3941d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 3941d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 3941d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3942d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3944d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4007d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4014d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4014d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4014d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4015d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4015d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4017d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4017d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 4017d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 4030d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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