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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 34

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Rev Log message Author Age Path
34 added vl_mux2_andor and vl_mux3_andor unneback 3792d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 3805d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3813d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 3832d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 3832d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 3832d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 3833d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 3833d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 3834d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 3835d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 3836d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 3836d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3837d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3838d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3902d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3908d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3909d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3909d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3909d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3910d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 3912d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 3912d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 3912d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 3925d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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