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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 40

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17 unneback 4240d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4246d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4247d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4247d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4248d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4248d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4250d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4250d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 4250d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 4263d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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