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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 43

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43 added logic for parity generation and check unneback 4986d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 4990d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 4991d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 4991d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 4991d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 4997d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 4999d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4999d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4999d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 5012d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 5020d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 5039d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 5039d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 5039d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 5040d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 5040d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 5041d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 5042d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 5043d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 5043d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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