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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 43

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21 reg -> wire in and or mux in logic unneback 3532d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3533d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3597d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3603d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3604d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3604d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 3604d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 3605d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 3607d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 3607d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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