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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 43

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21 reg -> wire in and or mux in logic unneback 4855d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4857d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4920d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4927d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4927d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4927d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4928d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 4929d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 4930d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 4930d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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