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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 46

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Rev Log message Author Age Path
46 updated parity unneback 4108d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 4109d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 4112d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43 added logic for parity generation and check unneback 4117d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 4121d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 4121d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 4122d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 4122d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 4127d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 4129d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4129d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4129d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 4142d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4150d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 4170d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 4170d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 4170d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 4171d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 4171d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 4171d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 4173d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4173d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4173d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4174d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4176d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4239d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4246d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4246d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4246d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 4247d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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