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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 48

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Rev Log message Author Age Path
48 wb updated unneback 4276d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 4372d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 4374d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 4377d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43 added logic for parity generation and check unneback 4381d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 4385d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 4385d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 4386d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 4386d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 4392d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 4393d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4394d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4394d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 4407d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4414d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 4434d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 4434d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 4434d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 4435d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 4435d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 4436d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 4437d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4438d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4438d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4439d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4440d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4504d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4510d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 4510d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 4510d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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