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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 48

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Rev Log message Author Age Path
48 wb updated unneback 3647d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 3744d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 3745d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 3748d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43 added logic for parity generation and check unneback 3752d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 3756d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 3757d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 3757d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 3757d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 3763d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 3765d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3765d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 3765d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 3778d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3786d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 3805d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 3805d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 3805d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 3806d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 3806d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 3807d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 3808d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 3809d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 3809d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 3810d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 3812d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 3875d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 3881d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 3882d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 3882d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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