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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 50

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50 added WB_B4RAM with byte enable unneback 4138d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
49 added WB_B4RAM with byte enable unneback 4138d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48 wb updated unneback 4145d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 4241d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 4243d 12h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 4246d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43 added logic for parity generation and check unneback 4250d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 4254d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 4254d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 4255d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 4255d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 4261d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 4262d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4263d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4263d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 4276d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4283d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 4303d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 4303d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 4303d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 4304d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 4304d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 4305d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 4306d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4307d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4307d 09h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4308d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4309d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4373d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4379d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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