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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 50

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28 added sync simplex FIFO unneback 4305d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 4305d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 4306d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 4307d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4308d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4308d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4309d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4310d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 4374d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 4380d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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