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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 52

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52 added WB_B4RAM with byte enable unneback 4883d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
51 added WB_B4RAM with byte enable unneback 4883d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
50 added WB_B4RAM with byte enable unneback 4883d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
49 added WB_B4RAM with byte enable unneback 4883d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48 wb updated unneback 4890d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 4986d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 4987d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 4990d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43 added logic for parity generation and check unneback 4995d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 4999d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 4999d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 5000d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 5000d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 5005d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
36 added generic andor_mux unneback 5007d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 5007d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
34 added vl_mux2_andor and vl_mux3_andor unneback 5007d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
33 updated wb3wb3_bridge unneback 5020d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
32 added vl_pll for ALTERA (cycloneIII) unneback 5028d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
31 sync FIFO updated unneback 5048d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30 updated counter for level1 and level2 function unneback 5048d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29 updated counter for level1 and level2 function unneback 5048d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 5049d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 5049d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 5049d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 5051d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 5051d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 5051d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 5052d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 5054d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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