URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 53

Rev	Log message	Author	Age	Path
31	sync FIFO updated	unneback	4878d 06h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
30	updated counter for level1 and level2 function	unneback	4878d 06h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
29	updated counter for level1 and level2 function	unneback	4878d 06h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28	added sync simplex FIFO	unneback	4879d 07h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27	added sync simplex FIFO	unneback	4879d 07h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25	added sync FIFO	unneback	4879d 22h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24	added vl_dff_ce_set	unneback	4881d 06h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23	fixed port map error in async fifo 1r1w	unneback	4881d 21h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22	added binary counters	unneback	4882d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21	reg -> wire in and or mux in logic	unneback	4882d 22h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v