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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 60

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60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3856d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
59 added WB RAM B3 with byte enable unneback 3857d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
56 WB B4 RAM we fix unneback 3886d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
55 added WB_B4RAM with byte enable unneback 3889d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
54 added WB_B4RAM with byte enable unneback 3889d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
53 added WB_B4RAM with byte enable unneback 3889d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
52 added WB_B4RAM with byte enable unneback 3889d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
51 added WB_B4RAM with byte enable unneback 3889d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
50 added WB_B4RAM with byte enable unneback 3889d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
49 added WB_B4RAM with byte enable unneback 3889d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48 wb updated unneback 3895d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 3992d 00h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 3993d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 3996d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43 added logic for parity generation and check unneback 4000d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 4004d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 4004d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 4005d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 4005d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 4011d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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