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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 60

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60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3808d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
59 added WB RAM B3 with byte enable unneback 3809d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
56 WB B4 RAM we fix unneback 3838d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
55 added WB_B4RAM with byte enable unneback 3840d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
54 added WB_B4RAM with byte enable unneback 3840d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
53 added WB_B4RAM with byte enable unneback 3840d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
52 added WB_B4RAM with byte enable unneback 3840d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
51 added WB_B4RAM with byte enable unneback 3840d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
50 added WB_B4RAM with byte enable unneback 3840d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
49 added WB_B4RAM with byte enable unneback 3840d 14h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48 wb updated unneback 3847d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 3943d 13h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 3945d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 3948d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43 added logic for parity generation and check unneback 3952d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42 updated mux_andor unneback 3956d 10h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40 new build environment with custom.v added as a result file unneback 3956d 11h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39 added simple port prio based wb arbiter unneback 3957d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38 updated andor mux unneback 3957d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
37 corrected polynom with length 20 unneback 3963d 05h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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