URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 72

Rev	Log message	Author	Age	Path
49	added WB_B4RAM with byte enable	unneback	4705d 01h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48	wb updated	unneback	4711d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46	updated parity	unneback	4807d 23h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45	updated timing in io models	unneback	4809d 18h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44	added target independet IO functionns	unneback	4812d 17h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43	added logic for parity generation and check	unneback	4816d 21h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42	updated mux_andor	unneback	4820d 20h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40	new build environment with custom.v added as a result file	unneback	4820d 22h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39	added simple port prio based wb arbiter	unneback	4821d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
38	updated andor mux	unneback	4821d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v