URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 73

Rev	Log message	Author	Age	Path
50	added WB_B4RAM with byte enable	unneback	4707d 09h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
49	added WB_B4RAM with byte enable	unneback	4707d 09h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48	wb updated	unneback	4714d 03h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46	updated parity	unneback	4810d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45	updated timing in io models	unneback	4812d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44	added target independet IO functionns	unneback	4815d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
43	added logic for parity generation and check	unneback	4819d 05h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
42	updated mux_andor	unneback	4823d 05h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
40	new build environment with custom.v added as a result file	unneback	4823d 06h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
39	added simple port prio based wb arbiter	unneback	4824d 03h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v