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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 79

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Rev Log message Author Age Path
79 avalon read write unneback 3757d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
78 default to length = 1 unneback 3757d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
77 bridge update unneback 3757d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
75 added wb to avalon bridge unneback 3757d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
73 no arbiter in wb_b3_ram_be unneback 3765d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
72 no arbiter in wb_b3_ram_be unneback 3765d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
71 no arbiter in wb_b3_ram_be unneback 3765d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
70 no arbiter in wb_b3_ram_be unneback 3765d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
69 no arbiter in wb_b3_ram_be unneback 3765d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
68 ram_be updated to optional mem_size unneback 3765d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
67 support up to 8 wbm on arbiter unneback 3766d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
66 RAM_BE ack_o vector unneback 3804d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
65 RAM_BE system verilog version unneback 3804d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
64 SPR reset value unneback 3804d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3804d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3804d 20h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3806d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
59 added WB RAM B3 with byte enable unneback 3807d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
56 WB B4 RAM we fix unneback 3836d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
55 added WB_B4RAM with byte enable unneback 3838d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
54 added WB_B4RAM with byte enable unneback 3838d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
53 added WB_B4RAM with byte enable unneback 3838d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
52 added WB_B4RAM with byte enable unneback 3838d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
51 added WB_B4RAM with byte enable unneback 3838d 22h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
50 added WB_B4RAM with byte enable unneback 3838d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
49 added WB_B4RAM with byte enable unneback 3838d 23h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
48 wb updated unneback 3845d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
46 updated parity unneback 3941d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
45 updated timing in io models unneback 3943d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
44 added target independet IO functionns unneback 3946d 15h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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