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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 94

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68 ram_be updated to optional mem_size unneback 4613d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
67 support up to 8 wbm on arbiter unneback 4614d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
66 RAM_BE ack_o vector unneback 4652d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
65 RAM_BE system verilog version unneback 4652d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
64 SPR reset value unneback 4652d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4652d 07h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4652d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4654d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
59 added WB RAM B3 with byte enable unneback 4655d 03h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
56 WB B4 RAM we fix unneback 4684d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

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