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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 100

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70 no arbiter in wb_b3_ram_be unneback 4725d 16h /versatile_library/trunk/rtl/verilog/wb.v
69 no arbiter in wb_b3_ram_be unneback 4725d 16h /versatile_library/trunk/rtl/verilog/wb.v
68 ram_be updated to optional mem_size unneback 4725d 16h /versatile_library/trunk/rtl/verilog/wb.v
67 support up to 8 wbm on arbiter unneback 4726d 16h /versatile_library/trunk/rtl/verilog/wb.v
66 RAM_BE ack_o vector unneback 4764d 15h /versatile_library/trunk/rtl/verilog/wb.v
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4764d 16h /versatile_library/trunk/rtl/verilog/wb.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4764d 16h /versatile_library/trunk/rtl/verilog/wb.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4766d 12h /versatile_library/trunk/rtl/verilog/wb.v
59 added WB RAM B3 with byte enable unneback 4767d 12h /versatile_library/trunk/rtl/verilog/wb.v
56 WB B4 RAM we fix unneback 4796d 11h /versatile_library/trunk/rtl/verilog/wb.v

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