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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 36

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Rev Log message Author Age Path
33 updated wb3wb3_bridge unneback 4823d 22h /versatile_library/trunk/rtl/verilog/wb.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4831d 08h /versatile_library/trunk/rtl/verilog/wb.v
18 naming convention vl_ unneback 4857d 07h /versatile_library/trunk/rtl/verilog/wb.v
17 unneback 4920d 20h /versatile_library/trunk/rtl/verilog/wb.v
14 reg -> wire for various signals unneback 4927d 09h /versatile_library/trunk/rtl/verilog/wb.v
13 cosmetic update unneback 4927d 10h /versatile_library/trunk/rtl/verilog/wb.v
12 added wishbone comliant modules unneback 4928d 06h /versatile_library/trunk/rtl/verilog/wb.v

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