URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 46

Rev	Log message	Author	Age	Path
44	added target independet IO functionns	unneback	4822d 06h	/versatile_library/trunk/rtl/verilog/wb.v
42	updated mux_andor	unneback	4830d 09h	/versatile_library/trunk/rtl/verilog/wb.v
40	new build environment with custom.v added as a result file	unneback	4830d 11h	/versatile_library/trunk/rtl/verilog/wb.v
39	added simple port prio based wb arbiter	unneback	4831d 08h	/versatile_library/trunk/rtl/verilog/wb.v
33	updated wb3wb3_bridge	unneback	4852d 02h	/versatile_library/trunk/rtl/verilog/wb.v
32	added vl_pll for ALTERA (cycloneIII)	unneback	4859d 12h	/versatile_library/trunk/rtl/verilog/wb.v
18	naming convention vl_	unneback	4885d 10h	/versatile_library/trunk/rtl/verilog/wb.v
17		unneback	4949d 00h	/versatile_library/trunk/rtl/verilog/wb.v
14	reg -> wire for various signals	unneback	4955d 13h	/versatile_library/trunk/rtl/verilog/wb.v
13	cosmetic update	unneback	4955d 14h	/versatile_library/trunk/rtl/verilog/wb.v
12	added wishbone comliant modules	unneback	4956d 10h	/versatile_library/trunk/rtl/verilog/wb.v