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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 48

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Rev Log message Author Age Path
48 wb updated unneback 4218d 20h /versatile_library/trunk/rtl/verilog/wb.v
44 added target independet IO functionns unneback 4319d 18h /versatile_library/trunk/rtl/verilog/wb.v
42 updated mux_andor unneback 4327d 22h /versatile_library/trunk/rtl/verilog/wb.v
40 new build environment with custom.v added as a result file unneback 4327d 23h /versatile_library/trunk/rtl/verilog/wb.v
39 added simple port prio based wb arbiter unneback 4328d 20h /versatile_library/trunk/rtl/verilog/wb.v
33 updated wb3wb3_bridge unneback 4349d 15h /versatile_library/trunk/rtl/verilog/wb.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4357d 00h /versatile_library/trunk/rtl/verilog/wb.v
18 naming convention vl_ unneback 4382d 23h /versatile_library/trunk/rtl/verilog/wb.v
17 unneback 4446d 13h /versatile_library/trunk/rtl/verilog/wb.v
14 reg -> wire for various signals unneback 4453d 01h /versatile_library/trunk/rtl/verilog/wb.v
13 cosmetic update unneback 4453d 03h /versatile_library/trunk/rtl/verilog/wb.v
12 added wishbone comliant modules unneback 4453d 23h /versatile_library/trunk/rtl/verilog/wb.v

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