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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Rev 48

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Rev Log message Author Age Path
48 wb updated unneback 3369d 02h /versatile_library/trunk/rtl/verilog/wb.v
44 added target independet IO functionns unneback 3470d 01h /versatile_library/trunk/rtl/verilog/wb.v
42 updated mux_andor unneback 3478d 04h /versatile_library/trunk/rtl/verilog/wb.v
40 new build environment with custom.v added as a result file unneback 3478d 06h /versatile_library/trunk/rtl/verilog/wb.v
39 added simple port prio based wb arbiter unneback 3479d 03h /versatile_library/trunk/rtl/verilog/wb.v
33 updated wb3wb3_bridge unneback 3499d 21h /versatile_library/trunk/rtl/verilog/wb.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3507d 07h /versatile_library/trunk/rtl/verilog/wb.v
18 naming convention vl_ unneback 3533d 05h /versatile_library/trunk/rtl/verilog/wb.v
17 unneback 3596d 19h /versatile_library/trunk/rtl/verilog/wb.v
14 reg -> wire for various signals unneback 3603d 08h /versatile_library/trunk/rtl/verilog/wb.v
13 cosmetic update unneback 3603d 09h /versatile_library/trunk/rtl/verilog/wb.v
12 added wishbone comliant modules unneback 3604d 05h /versatile_library/trunk/rtl/verilog/wb.v

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