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Rev Log message Author Age Path
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5041d 13h /
25 added sync FIFO unneback 5042d 03h /
24 added vl_dff_ce_set unneback 5043d 11h /
23 fixed port map error in async fifo 1r1w unneback 5044d 01h /
22 added binary counters unneback 5044d 06h /
21 reg -> wire in and or mux in logic unneback 5045d 03h /
20 naming convention vl_ unneback 5046d 13h /
19 naming convention vl_ unneback 5046d 13h /
18 naming convention vl_ unneback 5046d 14h /
17 unneback 5110d 03h /
16 converting utility for ROM unneback 5110d 14h /
15 added delay line unneback 5116d 11h /
14 reg -> wire for various signals unneback 5116d 16h /
13 cosmetic update unneback 5116d 17h /
12 added wishbone comliant modules unneback 5117d 13h /
11 async fifo simplex unneback 5118d 04h /
10 added dff_ce_clear unneback 5120d 03h /
9 added dff_ce_clear unneback 5120d 03h /
8 added dff_ce_clear unneback 5120d 03h /
7 mem update unneback 5120d 04h /

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