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Rev Log message Author Age Path
27 added sync simplex FIFO unneback 4852d 18h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4852d 20h /
25 added sync FIFO unneback 4853d 09h /
24 added vl_dff_ce_set unneback 4854d 17h /
23 fixed port map error in async fifo 1r1w unneback 4855d 08h /
22 added binary counters unneback 4855d 13h /
21 reg -> wire in and or mux in logic unneback 4856d 09h /
20 naming convention vl_ unneback 4857d 20h /
19 naming convention vl_ unneback 4857d 20h /
18 naming convention vl_ unneback 4857d 20h /
17 unneback 4921d 09h /
16 converting utility for ROM unneback 4921d 21h /
15 added delay line unneback 4927d 17h /
14 reg -> wire for various signals unneback 4927d 22h /
13 cosmetic update unneback 4928d 00h /
12 added wishbone comliant modules unneback 4928d 20h /
11 async fifo simplex unneback 4929d 11h /
10 added dff_ce_clear unneback 4931d 10h /
9 added dff_ce_clear unneback 4931d 10h /
8 added dff_ce_clear unneback 4931d 10h /
7 mem update unneback 4931d 11h /
6 added library files unneback 4944d 11h /
5 memories added unneback 4944d 11h /
4 added counters unneback 4948d 15h /
3 various updates
counter added
unneback 4951d 10h /
2 initial check-in unneback 4952d 11h /
1 The project and the structure was created root 4957d 15h /

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