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Rev Log message Author Age Path
28 added sync simplex FIFO unneback 4181d 16h /
27 added sync simplex FIFO unneback 4181d 16h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4181d 17h /
25 added sync FIFO unneback 4182d 07h /
24 added vl_dff_ce_set unneback 4183d 15h /
23 fixed port map error in async fifo 1r1w unneback 4184d 05h /
22 added binary counters unneback 4184d 11h /
21 reg -> wire in and or mux in logic unneback 4185d 07h /
20 naming convention vl_ unneback 4186d 18h /
19 naming convention vl_ unneback 4186d 18h /
18 naming convention vl_ unneback 4186d 18h /
17 unneback 4250d 07h /
16 converting utility for ROM unneback 4250d 18h /
15 added delay line unneback 4256d 15h /
14 reg -> wire for various signals unneback 4256d 20h /
13 cosmetic update unneback 4256d 22h /
12 added wishbone comliant modules unneback 4257d 18h /
11 async fifo simplex unneback 4258d 08h /
10 added dff_ce_clear unneback 4260d 07h /
9 added dff_ce_clear unneback 4260d 07h /
8 added dff_ce_clear unneback 4260d 07h /
7 mem update unneback 4260d 08h /
6 added library files unneback 4273d 09h /
5 memories added unneback 4273d 09h /
4 added counters unneback 4277d 13h /
3 various updates
counter added
unneback 4280d 08h /
2 initial check-in unneback 4281d 09h /
1 The project and the structure was created root 4286d 13h /

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