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Rev Log message Author Age Path
28 added sync simplex FIFO unneback 4879d 03h /
27 added sync simplex FIFO unneback 4879d 03h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4879d 04h /
25 added sync FIFO unneback 4879d 17h /
24 added vl_dff_ce_set unneback 4881d 01h /
23 fixed port map error in async fifo 1r1w unneback 4881d 16h /
22 added binary counters unneback 4881d 21h /
21 reg -> wire in and or mux in logic unneback 4882d 17h /
20 naming convention vl_ unneback 4884d 04h /
19 naming convention vl_ unneback 4884d 04h /
18 naming convention vl_ unneback 4884d 04h /
17 unneback 4947d 18h /
16 converting utility for ROM unneback 4948d 05h /
15 added delay line unneback 4954d 01h /
14 reg -> wire for various signals unneback 4954d 07h /
13 cosmetic update unneback 4954d 08h /
12 added wishbone comliant modules unneback 4955d 04h /
11 async fifo simplex unneback 4955d 19h /
10 added dff_ce_clear unneback 4957d 18h /
9 added dff_ce_clear unneback 4957d 18h /
8 added dff_ce_clear unneback 4957d 18h /
7 mem update unneback 4957d 19h /
6 added library files unneback 4970d 19h /
5 memories added unneback 4970d 20h /
4 added counters unneback 4974d 23h /
3 various updates
counter added
unneback 4977d 19h /
2 initial check-in unneback 4978d 19h /
1 The project and the structure was created root 4983d 23h /

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