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Rev Log message Author Age Path
48 wb updated unneback 3638d 03h /
47 added help program for LFSR counters unneback 3733d 06h /
46 updated parity unneback 3734d 07h /
45 updated timing in io models unneback 3736d 01h /
44 added target independet IO functionns unneback 3739d 01h /
43 added logic for parity generation and check unneback 3743d 04h /
42 updated mux_andor unneback 3747d 04h /
41 typo in registers.v unneback 3747d 06h /
40 new build environment with custom.v added as a result file unneback 3747d 06h /
39 added simple port prio based wb arbiter unneback 3748d 03h /
38 updated andor mux unneback 3748d 03h /
37 corrected polynom with length 20 unneback 3753d 23h /
36 added generic andor_mux unneback 3755d 08h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3755d 19h /
34 added vl_mux2_andor and vl_mux3_andor unneback 3755d 19h /
33 updated wb3wb3_bridge unneback 3768d 21h /
32 added vl_pll for ALTERA (cycloneIII) unneback 3776d 07h /
31 sync FIFO updated unneback 3796d 03h /
30 updated counter for level1 and level2 function unneback 3796d 03h /
29 updated counter for level1 and level2 function unneback 3796d 03h /
28 added sync simplex FIFO unneback 3797d 04h /
27 added sync simplex FIFO unneback 3797d 04h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3797d 06h /
25 added sync FIFO unneback 3797d 19h /
24 added vl_dff_ce_set unneback 3799d 03h /
23 fixed port map error in async fifo 1r1w unneback 3799d 17h /
22 added binary counters unneback 3799d 23h /
21 reg -> wire in and or mux in logic unneback 3800d 19h /
20 naming convention vl_ unneback 3802d 06h /
19 naming convention vl_ unneback 3802d 06h /

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