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Rev Log message Author Age Path
50 added WB_B4RAM with byte enable unneback 4136d 04h /
49 added WB_B4RAM with byte enable unneback 4136d 04h /
48 wb updated unneback 4142d 22h /
47 added help program for LFSR counters unneback 4238d 01h /
46 updated parity unneback 4239d 03h /
45 updated timing in io models unneback 4240d 21h /
44 added target independet IO functionns unneback 4243d 21h /
43 added logic for parity generation and check unneback 4248d 00h /
42 updated mux_andor unneback 4252d 00h /
41 typo in registers.v unneback 4252d 01h /
40 new build environment with custom.v added as a result file unneback 4252d 02h /
39 added simple port prio based wb arbiter unneback 4252d 23h /
38 updated andor mux unneback 4252d 23h /
37 corrected polynom with length 20 unneback 4258d 19h /
36 added generic andor_mux unneback 4260d 04h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4260d 15h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4260d 15h /
33 updated wb3wb3_bridge unneback 4273d 17h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4281d 03h /
31 sync FIFO updated unneback 4300d 22h /
30 updated counter for level1 and level2 function unneback 4300d 23h /
29 updated counter for level1 and level2 function unneback 4300d 23h /
28 added sync simplex FIFO unneback 4302d 00h /
27 added sync simplex FIFO unneback 4302d 00h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4302d 01h /
25 added sync FIFO unneback 4302d 15h /
24 added vl_dff_ce_set unneback 4303d 22h /
23 fixed port map error in async fifo 1r1w unneback 4304d 13h /
22 added binary counters unneback 4304d 18h /
21 reg -> wire in and or mux in logic unneback 4305d 14h /

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