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Rev Log message Author Age Path
65 RAM_BE system verilog version unneback 4674d 06h /
64 SPR reset value unneback 4674d 06h /
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4674d 06h /
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4674d 07h /
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4674d 07h /
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4676d 02h /
59 added WB RAM B3 with byte enable unneback 4677d 02h /
58 corrected EXT unit, rewrite of FF1, FL1 unneback 4693d 09h /
57 corrected EXT unit, rewrite of FF1, FL1 unneback 4693d 09h /
56 WB B4 RAM we fix unneback 4706d 02h /
55 added WB_B4RAM with byte enable unneback 4708d 08h /
54 added WB_B4RAM with byte enable unneback 4708d 08h /
53 added WB_B4RAM with byte enable unneback 4708d 08h /
52 added WB_B4RAM with byte enable unneback 4708d 08h /
51 added WB_B4RAM with byte enable unneback 4708d 09h /
50 added WB_B4RAM with byte enable unneback 4708d 09h /
49 added WB_B4RAM with byte enable unneback 4708d 09h /
48 wb updated unneback 4715d 03h /
47 added help program for LFSR counters unneback 4810d 06h /
46 updated parity unneback 4811d 07h /
45 updated timing in io models unneback 4813d 02h /
44 added target independet IO functionns unneback 4816d 01h /
43 added logic for parity generation and check unneback 4820d 05h /
42 updated mux_andor unneback 4824d 04h /
41 typo in registers.v unneback 4824d 06h /
40 new build environment with custom.v added as a result file unneback 4824d 06h /
39 added simple port prio based wb arbiter unneback 4825d 03h /
38 updated andor mux unneback 4825d 03h /
37 corrected polynom with length 20 unneback 4831d 00h /
36 added generic andor_mux unneback 4832d 08h /

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