URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [bench/] - Rev 27

Rev	Log message	Author	Age	Path
27	added the missing wishbone_unused_address_c to my_project_pkg.vhd fixed the readdata_v error and added the missing "end if;" in wishbone_bfm_pkg.vhd fixed a range error in convert_pkg.vhd minor changes to vhdl_wb_tb_Usage_guide.docx	sinx	1671d 13h	/vhdl_wb_tb/trunk/bench/
23	added message output for wb_read(int,slv)	sinx	2087d 18h	/vhdl_wb_tb/trunk/bench/
20	fixed some locations where wishbone_address_width_c was used but wishbone_data_width_c is correct added some comments to function declaration for better understanding	sinx	2087d 18h	/vhdl_wb_tb/trunk/bench/
19	added some more example wb_reads and comments	sinx	2087d 18h	/vhdl_wb_tb/trunk/bench/
18	added handling for wb_bfm_in_s.tgd .err and .rty	sinx	2087d 18h	/vhdl_wb_tb/trunk/bench/
15	minor beautifying	sinx	2097d 13h	/vhdl_wb_tb/trunk/bench/
14	added keyword expansion to vhdl files	sinx	2097d 14h	/vhdl_wb_tb/trunk/bench/
9	removed external	sinx	2097d 15h	/vhdl_wb_tb/trunk/bench/
7	added external to project spi_master_slave for SPI master stimulator	sinx	2097d 16h	/vhdl_wb_tb/trunk/bench/
5	added documentation some minor cleanups	sinx	2098d 15h	/vhdl_wb_tb/trunk/bench/
4	minor refacturation updated file header descriptions	sinx	2098d 19h	/vhdl_wb_tb/trunk/bench/
3	deleted	sinx	2098d 20h	/vhdl_wb_tb/trunk/bench/
2	inital version	sinx	2099d 12h	/vhdl_wb_tb/trunk/bench/