URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] - Rev 27

Rev	Log message	Author	Age	Path
27	added the missing wishbone_unused_address_c to my_project_pkg.vhd fixed the readdata_v error and added the missing "end if;" in wishbone_bfm_pkg.vhd fixed a range error in convert_pkg.vhd minor changes to vhdl_wb_tb_Usage_guide.docx	sinx	1677d 10h	/vhdl_wb_tb/trunk/bench/vhdl/
23	added message output for wb_read(int,slv)	sinx	2093d 14h	/vhdl_wb_tb/trunk/bench/vhdl/
20	fixed some locations where wishbone_address_width_c was used but wishbone_data_width_c is correct added some comments to function declaration for better understanding	sinx	2093d 15h	/vhdl_wb_tb/trunk/bench/vhdl/
19	added some more example wb_reads and comments	sinx	2093d 15h	/vhdl_wb_tb/trunk/bench/vhdl/
18	added handling for wb_bfm_in_s.tgd .err and .rty	sinx	2093d 15h	/vhdl_wb_tb/trunk/bench/vhdl/
15	minor beautifying	sinx	2103d 10h	/vhdl_wb_tb/trunk/bench/vhdl/
14	added keyword expansion to vhdl files	sinx	2103d 11h	/vhdl_wb_tb/trunk/bench/vhdl/
5	added documentation some minor cleanups	sinx	2104d 12h	/vhdl_wb_tb/trunk/bench/vhdl/
4	minor refacturation updated file header descriptions	sinx	2104d 16h	/vhdl_wb_tb/trunk/bench/vhdl/
3	deleted	sinx	2104d 17h	/vhdl_wb_tb/trunk/bench/vhdl/
2	inital version	sinx	2105d 08h	/vhdl_wb_tb/trunk/bench/vhdl/