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Rev Log message Author Age Path
17 Fix bugs:
25-Jul-2008 LPC firmware writes must not insert wait-states.
22-Jul-2008 LPC DMA does not report READY+MORE for multi-byte transfers

Add feature:
23-Jul-2008 propagate Wishbone errors across LPC interface

Improve Testbench:
Ability to test multiple wait-states on LPC Peripheral Wishbone Master interface.
Check wbs_err_o from LPC Host.

Rebuild examples with the fixes above.		 hharte 5745d 15h /
16 Fix bug: Spec violation for multi-byte firmware accesses
Built with ISE 10.1		 hharte 5749d 20h /
15 fixed bug: Spec vviolation for multi-byte firmware amcesses:
the multi-byte firmware accesses incorrectly follow the multi-byte DMA algorithm and issue a SYNC sequence between each byte transferred. Instead, multi-byte firmware accesses should issue a single SYNC sequence following the transfer of the multi-byte data phase		 hharte 5749d 21h /
14 Update for Xilinx ISE 10.1 hharte 5750d 06h /
13 Add testbench for serirq. hharte 5883d 06h /
12 Add serirq support and add DCM block to de-skew LPC_CLK to off-board LPC device. hharte 5883d 20h /
11 Add Serial IRQ Support hharte 5883d 20h /
10 Added Serial IRQ information. hharte 5883d 20h /
9 Add example projects for PCI LPC Host and LPC 7-Segment Display. hharte 5888d 18h /
8 Added some details on LPC cycle type definitions, fixed some inconsistencies. hharte 5888d 19h /
7 Add example projects for PCI LPC Host and LPC 7-Segment Display. hharte 5889d 04h /
6 Clean up whitespace. hharte 5889d 05h /
5 Fix bug in LPC Host that was causing a 2nd LPC cycle because the wishbone cycle was not completely retired when going back to the idle state.
Also clean up whitespace.		 hharte 5889d 05h /
4 Adding .cvsignore files to ignore .svn directories. hharte 5891d 07h /
3 Initial checkin of source files hharte 5891d 14h /
2 Initial version of documentation. hharte 5892d 14h /
1 Standard project directories initialized by cvs2svn. 5892d 14h /

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