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Rev Log message Author Age Path
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).		 dgisselq 3035d 07h /
85 Minor update/correction to operand B definition. dgisselq 3035d 07h /
84 Minor updates. dgisselq 3035d 07h /
83 Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)

Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)

Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true.		 dgisselq 3035d 07h /
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.		 dgisselq 3035d 07h /
81 Trying to clean up ISE generated warnings. dgisselq 3035d 07h /
80 Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining.		 dgisselq 3035d 07h /
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 3039d 11h /
78 Found/corrected annoying bug in floating point documentation of the opcode
table.		 dgisselq 3039d 11h /
77 First check-in: the test bench for the divide instruction. dgisselq 3040d 10h /

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