OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] - Rev 162

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2346d 06h /
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 2346d 06h /
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2361d 18h /
159 Now supports building a simulator that can load ELF files, such as GCC and/or
binutils will produce.
dgisselq 2361d 18h /
158 Now automatically builds the toolchain by default. dgisselq 2361d 18h /
157 Added the divide unit to the list of ZipCPU dependencies. dgisselq 2361d 18h /
156 Fixed a compiler warning for an unused result. dgisselq 2361d 18h /
155 Improved debug trace quality, for finding bugs after the fact. dgisselq 2361d 18h /
154 Added timing checks on the busy and valid signals: either one of the two is
valid, or the whole is idle.
dgisselq 2361d 18h /
153 Adds internal link functionality to the specification document format. dgisselq 2361d 18h /
152 Updated to match the new/updated multiply instructions. Of course, this is
still hand optimized and not compiled--so it's not really a true and proper
test (yet), but ... it's what I have.
dgisselq 2394d 16h /
151 Minor formatting change. dgisselq 2394d 16h /
150 Minor changes. dgisselq 2394d 16h /
149 Updated the Makefile documentation and the all target. dgisselq 2394d 16h /
148 Minor changes to get LONG_MPY working, and adjust the documentation. dgisselq 2394d 16h /
147 Cleans up div_tb a bit, causing it to write SUCCESS out if successful and
abort if not.
dgisselq 2394d 16h /
146 Fixes a problem where the assembler complained the compiler was trying to
move .org backwards. This is now fixed.
dgisselq 2394d 16h /
145 This fixes the pipelined memory problem that was introduced a while back to
fix ... pipelined memory conflicts. This appears to maintain the success
of the fix, while recovering the pipeline memory performance that was had
before.
dgisselq 2394d 17h /
144 Makes the auto-reload capability a configuration option, and fills out the
reset so that it is properly implemented.
dgisselq 2394d 17h /
143 This section belatedly adjusts the zasm assembler so that it can handle
the LONG_MPY changes that have taken place. However, the test.S assembler
test script is still not properly testing the multiplies--at least it will
succeed on everything else.
dgisselq 2394d 17h /
142 Bug fix--fixes some problems with conditional execution, as well as removing
an unnecessary peephole optimization.
dgisselq 2395d 17h /
141 Fixes two bugs: one causing merged strings in the read only string section to
be referenced at the wrong address, and the second which caused the assembler
to fail at SYMBOL-OFFSET references.
dgisselq 2395d 17h /
140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 2398d 06h /
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.
dgisselq 2401d 03h /
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.
dgisselq 2401d 03h /
137 This should (again) fix the bug of trying to build optest.cpp. dgisselq 2414d 21h /
136 Oops --- missed a couple HOST_WIDE_INT values in a printf. This casts them
to (long), so that we can work on both PC's and ARMs.
dgisselq 2414d 21h /
135 Replaced all occurrences of INTVAL(...) on printf lines with (long)INTVAL(...).
This should fix the problems zip-gcc was having while running on the ARM.
dgisselq 2414d 21h /
134 Working updates, to keep this up to date with the RTL code. dgisselq 2415d 18h /
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.
dgisselq 2415d 18h /

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.