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Rev Log message Author Age Path
171 This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters.		 dgisselq 2775d 10h /
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.		 dgisselq 2785d 04h /
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2821d 04h /
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.		 dgisselq 2834d 04h /
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.		 dgisselq 2834d 04h /
166 Bugfix version. This fixes a problem whereby function addresses with offsets
were not properly calculated, together with properly setting up pcrelative
offsets when using the move function together with a label.		 dgisselq 2834d 08h /
165 Added a test to make certain that the arithmetic right shift was properly
propagating the high order bit. (The test works under verilator, but didn't
initially work in Xilinx -- thus a difference between the two.)		 dgisselq 2834d 08h /
164 Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU.		 dgisselq 2842d 10h /
163 Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set!		 dgisselq 2850d 12h /
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2850d 12h /

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