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Rev Log message Author Age Path
192 Fixed a bug with constant alignment in the assembler. dgisselq 2279d 02h /
191 Updated toolchain, more information on the example debugger. dgisselq 2294d 05h /
190 Added the copyright statement back in. dgisselq 2295d 21h /
189 Final, as delivered, ORCONF slides. dgisselq 2295d 21h /
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
dgisselq 2327d 23h /
187 Updated to match changed register definitions within the core. dgisselq 2327d 23h /
186 Now allows profile dumping for ELF executables. dgisselq 2327d 23h /
185 Now includes the proper flags for building with ELF executable file support. dgisselq 2327d 23h /
184 Adjusted the illegal instruction option documentation. dgisselq 2327d 23h /
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2328d 00h /
182 Bug fix for fast memories. This now works for memories with single cycle
dgisselq 2328d 00h /
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2328d 00h /
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2328d 00h /
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2328d 00h /
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
dgisselq 2328d 00h /
177 Fixed the illegal address logic to be more precise. dgisselq 2328d 00h /
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
dgisselq 2328d 00h /
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2328d 00h /
174 Simplified the divide to improve timing performance. dgisselq 2328d 00h /
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2328d 00h /

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