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Rev Log message Author Age Path
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1786d 16h /
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.
dgisselq 1885d 23h /
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.
dgisselq 1911d 11h /
198 Added a copyright notice. dgisselq 1912d 16h /
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 1912d 16h /
196 Updated internal documentation. dgisselq 1912d 16h /
195 Adds a new mode that can handle a delayed stall signal. dgisselq 1912d 16h /
194 Cleaned up some parameters, trying to create more consistency. dgisselq 1912d 16h /
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 1912d 16h /
192 Fixed a bug with constant alignment in the assembler. dgisselq 1912d 16h /
191 Updated toolchain, more information on the example debugger. dgisselq 1927d 19h /
190 Added the copyright statement back in. dgisselq 1929d 11h /
189 Final, as delivered, ORCONF slides. dgisselq 1929d 11h /
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger.
dgisselq 1961d 13h /
187 Updated to match changed register definitions within the core. dgisselq 1961d 14h /
186 Now allows profile dumping for ELF executables. dgisselq 1961d 14h /
185 Now includes the proper flags for building with ELF executable file support. dgisselq 1961d 14h /
184 Adjusted the illegal instruction option documentation. dgisselq 1961d 14h /
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 1961d 14h /
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.
dgisselq 1961d 14h /

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