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Rev Log message Author Age Path
184 Adjusted the illegal instruction option documentation. dgisselq 2079d 23h /
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2079d 23h /
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.
dgisselq 2079d 23h /
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2079d 23h /
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2079d 23h /
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2079d 23h /
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs.
dgisselq 2079d 23h /
177 Fixed the illegal address logic to be more precise. dgisselq 2079d 23h /
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed.
dgisselq 2079d 23h /
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2079d 23h /

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