OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] - Rev 206

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
206 Updated assembler, fixes several bugs, adds better bug detection and reporting (fixes some segfaults on bugs) dgisselq 2556d 23h /
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 2556d 23h /
204 Added the two simulators back into the SVN repository dgisselq 2575d 18h /
203 Removed the (now unused) old GCC compiler, v5.3.0 dgisselq 2575d 18h /
202 Additional ZipCPU changes associated w 8b upgrade dgisselq 2575d 19h /
201 RTL files for the 8-bit capable ZipCPU. dgisselq 2575d 20h /
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.
dgisselq 2675d 03h /
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.
dgisselq 2700d 16h /
198 Added a copyright notice. dgisselq 2701d 20h /
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 2701d 20h /
196 Updated internal documentation. dgisselq 2701d 20h /
195 Adds a new mode that can handle a delayed stall signal. dgisselq 2701d 20h /
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2701d 20h /
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 2701d 20h /
192 Fixed a bug with constant alignment in the assembler. dgisselq 2701d 20h /
191 Updated toolchain, more information on the example debugger. dgisselq 2716d 23h /
190 Added the copyright statement back in. dgisselq 2718d 15h /
189 Final, as delivered, ORCONF slides. dgisselq 2718d 15h /
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger.
dgisselq 2750d 17h /
187 Updated to match changed register definitions within the core. dgisselq 2750d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.