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Rev Log message Author Age Path
208 Add install and readme files, updated testb to capture initial variable status in Verilator dgisselq 1767d 21h /
207 Updated the ELF support, and divide test-bench. dgisselq 1767d 21h /
206 Updated assembler, fixes several bugs, adds better bug detection and reporting (fixes some segfaults on bugs) dgisselq 1767d 21h /
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 1767d 21h /
204 Added the two simulators back into the SVN repository dgisselq 1786d 16h /
203 Removed the (now unused) old GCC compiler, v5.3.0 dgisselq 1786d 16h /
202 Additional ZipCPU changes associated w 8b upgrade dgisselq 1786d 17h /
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1786d 18h /
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.
dgisselq 1886d 00h /
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.
dgisselq 1911d 13h /
198 Added a copyright notice. dgisselq 1912d 18h /
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 1912d 18h /
196 Updated internal documentation. dgisselq 1912d 18h /
195 Adds a new mode that can handle a delayed stall signal. dgisselq 1912d 18h /
194 Cleaned up some parameters, trying to create more consistency. dgisselq 1912d 18h /
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 1912d 18h /
192 Fixed a bug with constant alignment in the assembler. dgisselq 1912d 18h /
191 Updated toolchain, more information on the example debugger. dgisselq 1927d 21h /
190 Added the copyright statement back in. dgisselq 1929d 13h /
189 Final, as delivered, ORCONF slides. dgisselq 1929d 13h /

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